1. Field of the Invention
The present invention relates to a scanning format conversion circuit comprising a pure logic circuit to convert a progressive scanning format employed by the moving picture expert group (referred to hereinafter as MPEG) into a zig-zag scanning format and vice versa.
2. Description of the Prior Art
For the efficient compression of a video signal, the MPEG employs discrete cosine transform (referred to hereinafter as DCT), quantization, variable length code (referred to hereinafter as VLC) and motion vector estimation techniques.
The DCT technique is adapted to produce a two-dimensional array of DCT coefficients according to a spatial frequency characteristic. In the two-dimensional array of DCT coefficients, higher frequency components are diagonally distributed to the lower right hand side beginning with the upper left hand side in which the lowest frequency component is present. The DCT coefficients can be expressed as several values by the quantization technique. The statistically quantized DCT coefficient values which are not "0" are mostly distributed at a lower frequency domain, whereas the values of "0" frequently appear at a higher frequency domain.
The VLC technique is adapted to scan the quantized DCT coefficient values to produce codes in the form of pairs: run R and length L. The run R indicates the number of times that "0" appears and the length L indicates the quantized DCT coefficient value.
Because the frequency components are diagonally advanced from the lower frequency domain to the higher frequency domain and the values of "0" frequently appear in such a direction, it is much more efficient in the data compression technique to perform the coding operation using a zig-zag scanning manner rather than a progressive scanning manner.
Therefore, the MPEG proposes that the coding and decoding operations be performed through the mutual conversion between a progressive scanning format and a zig-zag scanning format.
FIG. 1 is a view illustrating a two-dimensional array of 4.times.4 DCT coefficients, and FIG. 2 is a view illustrating the order when the DCT coefficients in FIG. 1 are scanned in the zig-zag manner.
Generally, the scanning format conversion signifies the conversion between the data orders in FIGS. 1 and 2.
A variable length coder requires an address generator for reading DCT coefficients from a memory in the zig-zag scanning order, whereas a variable length decoder requires an address generator for writing data of the zig-zag scanning format into a memory in the progressive scanning order. In result, the address generator signifies a scanning format conversion circuit.
The address generator is implemented using a read only memory (referred to hereinafter as ROM) table in which the scanning order is stored. In other words, data in the ROM table is used as an address for reading or writing data from or into a random access memory (referred to hereinafter as RAM). However, the ROM table acts merely to map data. For this reason, the address generator is high in its processing speed, but not suitable to the implementation of application specific integrated circuit (referred to hereinafter as ASIC).